By interleaving Renesas' low power, high sample rate ADCs, it is possible to achieve a combination of ultra-high sample rate and very high dynamic range that is not available in today’s stand-alone ADCs.
This reference design demonstrates the performance attainable by combining Renesas' ADC technology and SP Devices' interleaving algorithms. In this design, four ISLA112P50 12-bit, 500MSPS analog-to-digital converters are interleaved to sample at a rate of 2.0GSPS. At this sampling rate, the reference design provides over 6dB more SNR and 13dB better SFDR than the best alternative stand-alone ADC.
Reference design (RD) is a dual-band, triple-mode CDMA front-end to a receiver whose frequency plan requires digital and AMPS analog IFs to be at 183.6MHz. RD uses the MAX2338, a low-noise amplifier (LNA) with mixer, that is useful for TDMA, GSM, EDGE, and WCDMA applications.
The STEVAL-ILL089V1 evaluation board is based on the ALED6000 monolithic current source for high power LED driving. Digital dimming is implemented by driving the dedicated DIM pin. Low drop-out operation with almost 100% duty cycle can be achieved.